Design Methodologies For Low Power And High Speed Full Adder

Abstract

In this paper, different techniques involved in designing high performance with minimum power consuming full adder circuits are discussed and compared. Full adder plays an important role in portable digital applications such as PDAs, mobile phones, DSPs and address calculation for cache or memory accesses. It is one of the critical element in any digital communication device as there is a basic role of addition in all arithmetic circuits present in these electronic devices. However, as there is a limited amount of power available for the portable battery operated devices, the amount of power consumed by full adders is to be reduced and accordingly high performance is to be achieved.